Our client is a company in full growth offering unique wireless transceiver technology and innovation that achieves superior energy efficiency. They are currently looking for a DSP design engineer to join their team.

Under the supervision of the Chief Engineer, the RTL ASIC Design Engineer is a key member of the IC design team, researching, designing and bringing next-generation wireless transceivers into production at high volume.

• Design of digital blocks in VHDL and Verilog from specification to functional module. 
• Simulation of block functionality in Python and Matlab. 
• Produce technical documentation (block diagrams, etc.) & technical reports. 
• Verify designs to ensure a successful tape-out.   
• Support the testing and debugging of issues that may arise from early development stages through productization.   
• Work with the production teams through the development phase and optimizing the designs for increased manufacturing efficiency.  
• Work with the system group to define the requirements for digital and baseband blocks based on the system requirements.  

• Electrical Engineering degree with a minimum of 3 years of experience in digital RTL design (M.Eng. preferred)  
• Validated working experience in using VHDL and Verilog to translate block specifications into functional RTL. 
• Excellent programming skills in Python and Matlab, geared towards Digital Signal Processing. 
• Experience in wireless baseband modem design is an asset.
• Experience in Cadence or Synopsys digital design flow. 
• Strong understanding of digital design principles. 
• Ability to collaborate with multi-disciplinary teams. 
• Tenacity and propensity to do what it takes to deliver results and meet delivery dates. 
• Bilingual English/French an asset 

• Permanent, full time;
• Salary between 100 000$ and 120 000$ based on experience;
• Hybrid teleworking;
• Possibility to work in Montreal or Ottawa